Today, the logic self-test of ICs with high-speed clocks is mainly performed by using slow speed synchronized clocks. This means that a common test clock is used for all clock systems existed on an IC. Typically, this common test clock is derived from the JTAG (Joint Test Action Group) clock named TCK. (JTAG is the common name for what was later standardized as the IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture). The use of a common test clock is satisfactory for testing e.g., “stuck-at” faults, but it is not sufficient for testing “open” faults or “path-delay” faults. The latter category of faults requires at least two high-speed clocks during the capture phase (or capture cycles or periods) of a logic test. Thus, the use of a common test clock is not suitable for many applications. Some conventional technologies activate all high speed clocks during the capture phase. While it may detect “open” and “path-delay” faults, this approach can lead to unexplainable values being captured if interferences exist between some of the high speed clock systems.
Some other conventional technologies activate one high speed clock at a time to avoid the interferences between different clock systems. The test time for this approach, however, is unnecessarily long. Moreover, the fault coverage is low due to the use of a single clock as explained above. Still some other conventional technologies may allow multiple different clock frequencies activated during a test, but these different clock frequencies must be a multiple of a single high speed clock, which limits their applications. In addition, conventional technologies lack on-chip hardware that supports a glitch free switching from slow speed clocks during the shift phase to high speed clocks during the capture phase.